Graphics processors commonly include parallel processors for improving processing speed. In some prior art systems, each parallel processor processes data for a relatively large preselected contiguous portion of a display device. For example, in a four parallel processor graphics accelerator, each processor may produce pixel data for one quadrant of the display device. Accordingly, when an image to be drawn is substantially within one of the quadrants of the display, only one processor is processing while the other processors remain relatively dormant. This can significantly slow system speed, thus decreasing system efficiency.
To display a graphical image, data produced by each parallel processor must be transmitted to the display device. To that end, many prior art systems require that each parallel processor transmit pixel data to a single collection point (e.g., a part of the display device or some intermediate data collection device). Typical single collection points have an interface that can receive the data from each processor. In many such systems, the interface has a dedicated connection to each parallel processor. For example, in an eight processor system that produces twenty-four bits of data per clock cycle, the single collection point interface must have 192 pins to receive the data (i.e., the sum of the output of all the processors per clock cycle). Requiring such a large number of pins, however, undesirably requires a relatively large surface area, increases the cost and complexity of the interface, and decreases system efficiency.